I’m getting back to this interface and looking more closely at the signaling between the XSi and 580ex flash. This is a continuance of the post: https://billgrundmann.wordpress.com/2009/03/04/ettl-interface/
I realized that I needed to look at how the flash informs the camera that it exists and is turned on.
This picture shows “D1” from the camera (on top) and the leading edge of “CLK” from the camera (on bottom). It looks like the flash informs the camera of its “on” status by pulsing high right after the clock goes high. This particular pulse starts about 1.6usec after the clock and last for about 11usec.
The flash also seems to indicate a ready concept using D1 as shown in the following picture. This is a capture of D1 (on top) and CLK (on bottom). D1 seems to go high before the camera starts to clock some data. D1 stays high until the clock drops and then, for this example, changes for the first bit of the clocked data (in this example the data bit is “0”. This D1 high before the clock is likely the flash ready to receive flag to the camera. This also means that if the last data bit, for the current clocked byte, is “1”, then D1 has to drop to “0” so that it can rise again as ready later.
The following picture shows a chain of clocked bytes from the flash (D1 on top, clock on bottom). Notice that D1 always goes high before the first clock of a new byte and then changes to whatever is the value of the first bit after CLK 1st falls. Notice also at the point marked with an “X”; this is a case where the last data bit is a “1” and D1 returns to zero and later returns to one to indicate ready for the next byte.
So, you can see that there is a handshake between the flash and camera. The camera can’t send another byte of data until the flash indicates it is ready to receive it.
I found no similar characteristics on the camera’s data, D2.